(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly to a method for integrating dynamic random access memory (DRAM) circuits with logic circuits. The method is particularly useful for integrating DRAM cells with field effect transistors (FETs) formed by the self-aligned silicide (SALICIDE) process. The DRAM process is compatible with the salicide process by reducing the thermal budget (time at temperature) required for processing the merged logic/DRAM chips. The method uses two levels of metal to concurrently form the DRAM capacitors and the metal interconnections for the logic, thereby providing a plane structure using a cost-effective process.
(2) Description of the Prior Art
Merged logic and memory circuits are finding extensive use in the electronics industry. These circuits, such as microprocessors, are used in the computer industry for general purpose computing. Merged integrated circuits are also used for application-specific circuits (ASC) in other industries, such as automobiles, toys, communications, the like.
To optimize these merged circuits, it is desirable in the electronics industry to fabricate the FETs for the logic and DRAM circuits having different processes and therefore different electrical parameters. For example, it is desirable to use a thin gate oxide for the logic FETs and the peripheral circuits for the DRAM FETs to increase performance (circuit speed), while it is desirable to use a thicker gate oxide, narrower sidewall spacers, and self-aligned contacts (SACs) for the FET access transistors of the DRAM memory cells because of the higher gate voltage (Vg), and also to achieve high density of memory cells and higher yield. It is desirable to integrate the logic and memory circuits on the same chip using shared process steps to minimize the manufacturing costs.
The process of choice for making the FETs for the logic circuits on the chip is to use the self-aligned silicide process (SALICIDE process) and to use tungsten silicide FET gate electrodes for the memory cell region. The SALICIDE process for the logic consists of forming a doped electrically conducting polysilicon layer which is patterned to form the FET gate electrodes over a thin gate oxide on the silicon substrate. Lightly doped drain (LDD) areas are formed adjacent to the gate-electrode regions, and insulating sidewall spacers are formed on the gate electrodes. A second implant is used to form the ohmic source/drain contacts in the substrate adjacent to the sidewalls. A thin metal layer, such as titanium (Ti), is deposited and annealed to form a TiSix on the exposed silicon surfaces of the gate electrodes and on the adjacent source/drain contact areas, The unreacted Ti on the insulating surfaces (e.g., silicon oxide) is selectively removed to complete the SALICIDE FETs.
When the channel length of the FET is reduced (currently to less than 0.18 micrometers) to improve circuit performance, it is necessary to use very shallow diffused junctions for the implanted source/drain areas and thin metal silicide contacts to avoid short channel effects, such as punchthrough. Unfortunately, in the current DRAM circuit of choice, the memory cells are fabricated using stacked capacitors which are formed over the memory cell areas after the SALICIDE FETs are completed. The conventional DRAM capacitors are formed using several layers of doped polysilicon which require high-temperature processing for extended periods of time that can electrically degrade the very shallow ( less than 0.1 um) implanted source/drain junctions and the thin TiSix contacts. Therefore, there is a strong need in the industry to fabricate DRAM stacked capacitors at reduced temperatures and/or shortened times (commonly referred to as the xe2x80x9cthermal budgetxe2x80x9d in the industry) to prevent degrading the narrow channel/shallow junction FET devices.
Numerous methods of forming logic circuits with embedded DRAM devices have been reported in the literature. One method of making merged or embedded DRAM devices with logic circuits is described in U.S. Pat. No. 5,858,831 to Sung. Sung""s method teaches a process for forming FETs for logic and for DRAMs having different gate oxide thicknesses, while minimizing the number of masking steps. Huang in U.S. Pat. No. 5,863,820 teaches a method for integrating DRAMs with self-aligned contacts and salicide FETs for logic on the same chip. Yoo et al. in U.S. Pat. No. 5,719,079 describe a method for making static RAM (SRAM) using a salicide process. However, none of the references addresses making low-temperature DRAMs embedded with logic circuits having salicide FETs.
Therefore there is still a need in the semi-conductor industry to fabricate embedded DRAM devices using a low thermal budge process to prevent electrical degradation of the salicide FETs while providing a cost-effective manufacturing process.
It is a principal object of the present invention to provide a method for forming embedded DRAM circuits that are compatible with high-performance self-aligned metal silicide FETs on logic circuits.
It is another object of the present invention to achieve the above objective by using a low-temperature process for fabricating the DRAM capacitors and concurrently forming the metal interconnections without excessive thermal budget that can degrade the salicide FETs.
Another object of the present invention to achieve the above objective is to make the DRAM capacitors utilizing metal layers that are deposited at lower temperatures and which are not achieved by the more conventional polysilicon process.
Yet another objective is to concurrently form the DRAM capacitors and the electrical interconnections to provide a cost-effective manufacturing process.
The method for integrating these metal DRAM capacitors with logic circuits having salicide FETs is now briefly described. As the circuit density increases to achieve high-performance circuits, it is necessary to use self-aligned silicide FETs having very shallow diffused junctions with silicide contacts. This necessitates using low-temperature processing for making the subsequent DRAM capacitors to prevent electrically degrading the salicide FETs.
After forming the salicide FETs for logic circuits and the FETs for the DRAM memory cells on a Pxe2x88x92 doped single-crystal silicon substrate, the method of completing the DRAM devices having capacitors formed by low-temperature processing begins by forming a planar first insulating layer, commonly referred to as an interlevel dielectric (ILD) layer, over the FETs on the substrate. First openings are etched in the planar first insulating layer to form the contact openings for contacts to the salicide FETs, and concurrently openings are etched for the bit-line contacts and capacitor node contacts in the memory regions. A metal layer, such as tungsten (W), is deposited and is polished or etched back to the first insulating layer to form metal plugs in the contact openings. A first metal layer, such as aluminum-copper (AlCu), is deposited at low temperature, for example by physical vapor deposition, and a silicon nitride (Si3N4) cap layer is deposited by plasma-enhanced chemical vapor deposition (PECVD) on the AlCu. The cap layer and the AlCu layer are patterned to form a first level of metal interconnections for the logic, and also to form the bit lines for the DRAM circuits. Next, a conformal Si3N4 layer is deposited and anisotropically etched back to form sidewall spacers on the metal interconnections. A relatively thick second insulating layer, such as silicon oxide (SiO2) or a borophosphosilicate glass (BPSG), is deposited at low temperature by PECVD, and is planarized over the metal interconnections and bit lines. The second insulating layer is commonly referred to as an intermetal dielectric (IMD) layer. Conventional photolithographic techniques and anisotropic plasma etching are used to etch second openings over and to the capacitor node contacts, and are self-aligned to the bit lines. Another masking step and plasma etching are used to etch via holes in the second insulating layer and in the Si3N4 cap layer to the first level of metal interconnections for the salicide FETS. A metal layer, such as tungsten (W), is deposited at low temperature by CVD using WF6 and H2 to fill the second openings and the via holes, and the metal is polished back to the surface of the second insulating layer to concurrently form capacitor bottom electrodes and W contacts in the via holes. Optionally, a photoresist mask and etching can now be used to recess the second insulating layer to the Si3N4 cap layer on the bit lines and around the bottom electrodes to increase surface area of the bottom electrodes thereby increasing capacitance. Continuing, an interelectrode dielectric layer, such as tantalum pentoxide or barium strontium titanium oxide is deposited at low temperature on the substrate, and is patterned to leave portions over the capacitor bottom electrodes. A second metal layer, such as AlCu, is deposited and patterned to form a second level of electrical interconnections and concurrently to form the capacitor top electrodes. Additional levels of IMD layers and metal interconnections are formed to complete the integrated circuit.